1. Field of the Invention
The present invention relates to oscillators and more specifically to the trimming of dual frequency integrated circuit (IC) oscillators.
2. Description of the Related Art
In the past, current has been used to control the speed of an integrated circuit oscillator. This has been accomplished with a circuit which uses the summing of a binary weighted current from a current mirror source to set an exact current to the oscillator. This invention provides a method which has been developed to optimize the trimming of this oscillator current.
FIG. 1 (related art) shows a current divide circuit used to implement the oscillator trim function. The general approach is to supply the reference oscillator current with a first current source and then to add binary weighted trim current from a second mirrored current source to generate the desired oscillator frequency. More specifically, current from the first current mirror 1-2 sets the normal reference oscillator current, while current from an identical current mirror 3-4 establishes the trim current which is binary weighted and added to the reference current. The binary trim is accomplished by means of a set of ratioed p-channel transistors 5-10 whose area (Lxc3x97W) is made to decrease in binary fashion from the most significant bit 10 to the least significant bit 5. These transistors act as binary weighted load resistors to control the trim current in each leg. For example, during the layout of these transistors a typical design would be as follows:
This ratio is set by the equation   ratio  =            Σ      ⁢              xe2x80x83            ⁢              T        w                    Σ      ⁢              xe2x80x83            ⁢              T                  w          ⁡                      (            on            )                              
where Tw is the total width of all the trim transistors 5-10 and Tw(on) is the width of the trim transistors 5-10 which are turned on. Additional sets of complementary transistor switches are used to control the paths for the trim current. Each of these switches consists of two p-channel transistors and an inverter configured so that when one transistor is turned ON the other is turned OFF, depending on the binary state of it""s input control line. In the circuit, transistors 11-16 are used to route the binary weight trim current through the ON bits to the output line and transistors 17-22 are used to route the binary weight trim current through the OFF bits to ground. Inverters 23-28 are wired to accomplish the complementary function of each switch set. In operation, input signals I1 and I2 are used to establish the reference and trim current in the two cascode current mirrors 1-2 and 3-4, respectively. The trim current is divided in binary fashion through transistors 5-10. Control lines C1-C6 are used to turn ON the desired complementary switches 11-16 and allow the binary weighted trim current Iout to flow in the output line. For the unused binary weighted bits, where the trim transistors are turned OFF, the corresponding shunt transistors 17-22 are turned ON to direct this current to ground. Therefore, by changing the control inputs in real time, the oscillator trim current can be controlled. Generally, these oscillators are trimmed by choosing a target setting and testing to see if the frequency is within tolerance and if so, assuming that the chosen value is adequate. However, such an approach seldom results in optimal trimming of the oscillator and often is just within tolerance and may drift out of spec during operation in a critical application.
FIG. 2 (related art) shows another version of the circuit which has been used to implement the trim function for dual frequency oscillators. This circuit not only supplies dual frequency trim, but conserves silicon area by sharing 4 of the 1 binary trim control bits between the two oscillator frequencies. In this circuit, a second cascode current mirror, made up of transistors 33-36, is added-to the first cascode mirror, made up of transistors 29-32. Transistors 29-30 provide the reference oscillator current and transistors 31-32 provide the binary trim current for the high frequency while transistors 33-34 provide the reference oscillator current and transistors 35-36 provide the binary trim current for the low frequency oscillator. As mentioned above, the 7 trim control bits are divided into 4-bits, used for coarse trim adjust, and 3-bits used for fine trim adjust. In operation, the coarse adjust bits are shared between the two oscillator frequencies, while the fine adjust bits are controlled separately for each of the two oscillator frequencies. Transistors 40-43 and 56-58 are used to establish the binary weighted trim current for the coarse and fine trim bits, respectively. The area (Lxc3x97W) of these transistors is scaled so as to decrease the current in each leg in a binary fashion, from most to least significant bit. Additional sets of complementary transistor switches are used to control the paths for the trim current. These switch pairs either select the binary weighted current from a bit, to be added as trim current to the oscillator or route unselected bit current to ground. Inverters are included in each switch pair so that when one transistor is turned ON the other is turned OFF, depending on the binary state of it""s input control line. For the coarse trim bits, transistors 44-47 are used to route the binary weighted trim current through the ON bits to the output line and transistors 48-51 are used to route the binary weighted trim current through the OFF bits to ground. Inverters 52-55 are wired to accomplish the complementary function of each switch set. Similarly for the fine trim bits, transistors 62-64 are used to route the binary weighted trim current through the ON bits to the output line and transistors 59-61 are used to route the binary weighted trim current through the OFF bits to ground. Inverters 65-67 are wired to accomplish the complementary function of each switch set.
The coarse bits are turned ON and OFF by control signals C4-C7, which the fine bits are selected by logic circuits made up of gates 68-70, 71-73, and 74-76 for bits C1-C3. This logic allows for the fine trim bits to be controlled individually for the high and low frequencies C1H and C1L, C2H and C2L, and C3H and C3L. Transistors 37-38 and inverter 39 are used to select high or low frequency operation for the fine trim circuitry. Due to the inverting nature of the fine bit control logic, opposite select transistors 62-64 are used relative to the coarse bits where transistors 44-47 are used. In operation, input signals I1 and I2 are used to establish the reference and trim current in the two cascode current mirrors. The trim current is divided in binary fashion through transistors 40-43 and 56-58. Control lines C1-C7 are used to turn ON the desired complementary switches 40-43 and 65-67 for the coarse and fine bits, respectively, and allow the binary weighted trim current Iout to flow in the output line. For the unused binary weighted bits, where the trim transistors are turned OFF, the corresponding shunt transistors 48-51 and 59-61 are turned ON to directed this current to ground. Therefore, by changing the control inputs in real time, the oscillator trim current can be controlled.
Generally, these oscillators are trimmed by choosing a target setting and testing to see if the frequency is within tolerance and if so, assuming that the chosen value is adequate. However, such an approach seldom results in optimal trimming of the oscillator and often is just barely within spec, and as a result may drift out of spec during operation. A method is needed to assure that these oscillators are optimally trimmed near the center of the specification range so as to provide reliable operation in critical applications.
This invention provides a method that optimally trims dual frequency oscillators. The approach also allows for portions of the trim circuitry to be shared between two frequencies, thereby reducing amount of integrated circuitry required.
A method for accurately trimming the frequency of dual frequency integrated circuit oscillators in real-time by setting the desired frequencies by means of on-chip fuses. This method chooses the optimal trim for both oscillators by picking trim values for the two frequencies using a combination of binary and linear searching techniques. Additional testing is then carried out to assure that the trimmed oscillators frequencies are optimally within specification. In operation, this approach breaks the adjustment bits into coarse and fine bits and makes the coarse bits common between the two frequencies, resulting in an overall savings of hardware. The fine adjustment bits are not commonly shared and therefore are controlled separately. This method compensates for the undesirable effect that the ratio between the two frequencies is not constant, but decreases as the coarse trim setting increases. This provides optimal trim of the two desired oscillators frequencies, for the given conditions of common coarse bits. Basically, this method performs a binary search to find the optimal coarse value which is closest to the center of the overlap in the four common coarse bits and then performs a linear search on the three separate fine bits to provide the two desired frequencies which are optimally within specification. The primary advantages of this invention are speed accuracy in setting the trim of the oscillators.
The use of this method has been shown to reduced the trim adjustment time by about 50% from 8 seconds to less than 4 seconds and improved the trim accuracy from as poor as xc2x12.5% to better than xc2x11.0%